1. Field of the Invention
The present invention relates to the field of test circuitry for integrated circuits or systems. More particularly, the present invention pertains to a novel method of testing a circuit using a reduced number of method steps, instructions and clock cycles.
2. Art Background
Various techniques have been developed to enable testing of a device, such as an integrated device, by including test logic into the device itself. The integrated test logic provides the ability to test the overall functionality of a particular device as well as a functional block (logic blocks, registers, I/O's etc.) within a particular device. Additionally, integrated test logic provides a way for testing interconnections between integrated circuits once the circuits have been assembled onto a printed circuit board (PCB) or other substrate, as well as, observing and modifying circuit activity during a device's normal operation.
One standardized approach to providing the test logic within a device is defined in IEEE Std 1149.1-1990 and 1149.1a-1993 entitled IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1). IEEE Std 1149.1 defines a test access port (TAP) which is a general purpose port that can provide access to many test support functions built into a component to be tested. The TAP has a minimum of three dedicated input connections: a Test Input Clock (TCK) for clocking in serial test data or instruction information, a Test Mode Select Input (TMS) which is decoded by logic accessing the TAP to control test operations, and Test Data Input (TDI) which provides serial input test data or instruction information. In addition, the TAP has at a minimum one dedicated output: Test Data Output (TDO) which provides for the serial output of data from the TAP. Through the use of the test logic accessed through the TAP, data, address and instruction information may be serially written to and read from a device under test.
FIG. 1 shows a single device under test configuration 10 in which test logic accessed through a TAP may be implemented. A device under test 12 may be a single integrated circuit device or a system on a PCB. Device under test 10 includes a test circuit 14 which receives serial test data input TDI 16, test input clock TCK 20, and test mode select TMS 22. Additionally test circuit 14 outputs serial test data output 18.
FIG. 2 shows a multiple devices under test configuration 100 and illustrates how components to be tested may be interconnected in a serial configuration in compliance with IEEE Std 1149.1. Specifically, device under test 102 is serially connected to device under test 104 through their respective test circuits 106 and 108. When test circuits 106 and 108 comprise test logic accessed through a TAP as illustrated in FIG. 2, test circuits 106 and 108 receive TCK 112 and TMS 114. Test data and instruction information is serially received by test circuit 106 from TDI 110 and is output as serial output data at node 118. The serial output data at node 118 is received by test circuit 108 and output as serial output data at TDO 116. Test circuits 106 and 108 may be distributed throughout devices under test 102 and 104.
FIG. 3 illustrates, in accordance with IEEE Std 1149.1, prior art test logic 200 for testing a component and using a TAP. Test logic 200 comprises controller 203 which includes control logic 202 coupled to decode control logic 204. Control logic 202 receives and interprets the signals on TMS 218 and TCK 220 and together with decode control logic 204 generates clock and/or control signals as required. A set of registers, including instruction register 206, data registers 208 and 210, boundary scan register 212 and bypass register 214, are configured to receive input signals from decode control logic 204, TCK 220 and TDI 222.
Through the interaction of control logic 202 and decode control logic 204 an instruction is serially loaded into instruction register 206 from TDI 222. With instruction register 206 comprising Z bits, it requires Z clock cycles of TCK 220 to load an instruction into instruction register 206. Instructions loaded into instruction register 206 are decoded by decode control logic 204 and are used to select a test to be performed and/or register to be accessed. Data register 208 which comprises X bits, and data register 210 which comprises Y bits, allow access to design-specific test support features in a device under test, such as self-test, scan paths, etc. Boundary scan register 212 allows testing of board interconnections, testing of typical production defects such as opens and shorts and allows access to component inputs and outputs. Bypass register 214 provides a one-bit serial connection for use when no other register is being used.
Additionally, test logic 200 includes a selector 216 which is controlled by a select signal at node 226 from decode control logic 204. Selector 216 receives the serially shifted out data from instruction register 206, data registers 208 and 210, boundary scan registers 212 and bypass register 214 and selectively outputs the received data at output TDO 224.
Test logic 200 has been utilized to test a device, such a programmable logic device, as illustrated in FIG. 8. At step 800, an instruction is serially shifted into instruction register 206 which instructs test logic 200 to load address information into data register 208. The address information indicates an address to be tested within the device under test. At step 802, the address information is serially shifted into data register 208. At step 804, an instruction is serially shifted into instruction register 206 which instructs test logic 200 to load data register 210 with a first data packet. At step 806, the first data packet is serially shifted into data register 210. At step 808, an instruction is serially shifted into instruction register 206 which instructs test logic 200 to program the address location stored in data register 208 with the first data packet stored in data register 210. At step 810, an instruction is serially shifted into instruction register 206 which instructs test logic 200 to read or capture a second data packet from the address location stored in data register 208 and store the captured second data packet into data register 210. This step verifies that the first data packet was correctly programmed into the address location stored in data register 208. Finally, at step 812, the data packet stored in data register 210 is serially shifted out from data register 210 through selector 216 to TDO 224.
The method of FIG. 8 requires a significant number of clock cycles in order to program a location in a device under test and to verify that the programming was completed correctly. Specifically, it requires 4Z+2Y+X clock cycles: 4Z clock cycles to load the four instructions in steps 800, 804, 808 and 810; 2Y clock cycles to execute steps 806 and 812; and X clock cycles to execute step 802. The more clock cycles that are used to test a device, the lower the testing throughput and the greater the likelihood that a false programming error will be introduced due to system noise. Additionally, the more instructions that are used in order to test a device, the lower the testing throughput.
Therefore, a need exists for a method of testing a device, which may incorporate test logic compatible with IEEE Std 1149.1, in a reduced number of method steps, reduced number of instructions and reduced number of clock cycles in order to increase testing throughput. Additionally, a need exists for a method of testing a device, which may incorporate test logic compatible with IEEE Std 1149.1, in a reduced number of clock cycles in order to reduce the number of false errors caused due to system noise.